“Custom chip” is the new buzzword. Everyone is getting into it. The big and the small. The public and the private. Companies that never built anything but software and companies that never built anything but gadgets. From one corner of the world to every other. The word is now everywhere, which is usually the first sign that it may have stopped meaning much.

Last year, we had an article talking about 2026’s Real Chip War. There, we argued the giants would build their own silicon, and that the point of building it was to stop renting so much of it from one vendor. We drew a comfortable line under that thought. A chip that could rival the best merchant GPU took the better part of a decade to develop, so the hyperscaler programs would grind forward without landing a quick blow. 

In Chip Design: Hardware’s Software, we split the industry into two. Design was the Office, contestable and cheap to enter at the edges. Manufacturing was the Plant, with tens of billions of dollars and tens of thousands of small, accumulated tricks; its barriers were closer to permanent.

Both pieces still stand. What neither saw coming was who would walk into the Office, aka announce their own custom chips, next. The latest announcers are not cloud operators, but they are model makers. In the space of a few weeks, OpenAI, Anthropic, Meta, DeepSeek and Zhipu have all reached for their own silicon at once.

Given how many are suddenly getting into custom chips globally, with many more likely to join soon, we need to look at the whole chip design space afresh to assess the reasons and consequences.

The word that hides more than it reveals

Open any week of announcements, and you will find “custom chip,” “ASIC,” “inference accelerator” and “custom silicon” used as if they named one object, sitting next to proper nouns like TPU and Jalapeño as though a name told you anything about what a thing does. It does not. The vocabulary collapsed just as the number of things it describes exploded.

A custom chip today is at least five broadly different categories wearing one description.

The last row is where the confusion compounds. When a famous consumer-electronics company signs a large “custom silicon” deal for the parts that let its gadgets reach Wi-Fi and cellular networks, the headline reads the same as one about a frontier inference accelerator released in the same week. It is not the same. One is a data center based on the economics of running models. The other is device connectivity, and its real driver is where the parts get made, not what they compute. 

Of course, the informed investors are well aware. But it is worth keeping the five rows in mind as we try to parse different types of AI-ASICs. Focusing on these differences has become important as we try to make sense of the barrage of announcements.

A short primer: Why AI keeps demanding custom silicon

Simplistically, a chip that runs an AI model has two halves that matter. One half does the math. The other half moves data to and from memory. In the first phase of AI computing history, say until around the middle of the last year, the processing part mattered more – and then that completely flipped.

In the earliest days of generative AI gaining in popularity, building a model mattered far more than running it. Training is enormously math-heavy. In the years when only a handful of labs trained models and few people used them, the math engine was the part that ran short. So that is what everyone chased: faster processors and more of the units that do arithmetic.

Then the models got good, and the world started using them. Every question put to a model has to be answered somewhere, billions of times a day, and answering is a very different job from building.

As usage exploded, running models swelled into the larger share of all the computing done, and building them shrank in relative terms. The bottleneck moved with it, off the math and onto memory. This is structural, not a passing phase, and it is why the pressure keeps building not only on memory and the links between chips, but on the whole case for customizing the silicon.

To produce a single word, the chip has to pull the entire model, hundreds of gigabytes of it, across a narrow path, and then do only a small amount of math with what arrives.

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So the math half sits mostly idle while the moving half is swamped. The jam is not in the doing. It is in the moving. And you cannot fix a jam like that by buying a faster engine, because the engine is no longer the problem. A fix needs a rearranging of the work so nothing sits waiting and nothing piles up. And, rearranging it is only possible if you know, in detail, the exact shape of the model you are running.

That is why this lands on the model makers. Nobody else knows their models well enough to decide what to move, what to keep close and what to skip.

The first place they rearrange is the logic chip.

The units that otherwise would be idle can be put to work with smart hardware-level customization. One effort is in keeping more of the data on the chip so it need not be fetched twice. The other is to work on the order, so the pieces arrive just in time. This would allow the spare capacity to help manage the traffic instead of waiting for it. A chip shaped to one model wastes far less than a general one.

The second place, slower to arrive and only now beginning, is the memory itself.

For decades, memory only stored data and handed it back. The pressure of inference is pushing it to do more: a little computing of its own, sending only what is actually needed, and managing the flow with tools built for one customer’s models.

Put the two together, and the direction is plain. As models grow heavier, the standard part, whether logic or memory, keeps making the jam worse, and the reward for shaping the silicon to the model keeps rising. That is why custom silicon is not a passing phase. It is a road, and we are still near the start of it.

One company, many chips

The freshest illustration arrived from Meta, and its whole importance is that it is not another accelerator. Meta disclosed a chip called Vistara, and it is not the cousin of Ironwood, Maia, Trainium or Meta’s own MTIA.

It does not run models at all. It is a memory manager, a small custom part that hangs cheap, decommissioned memory off a server as a slower, colder tier beneath the fast local memory, so that latency-tolerant work can spill into capacity that would otherwise have been thrown away.

Meta reckons it lets the fleet retire a quarter of the servers it would have needed. It solves a plumbing problem, not a math problem, and it is a sign of what is coming. Each large player will run not one custom chip but a growing fleet of them, accelerators and memory managers and networking parts and more, and similar moves will spread across every hyperscaler.

So when you read that a company “builds its own chip,” the sentence is already too vague to use. Which chip, and for which job?

The way to cut through it is to stop asking what a chip is and start asking what its maker owns, because that decides what it customizes.

The hyperscalers own the whole rack and the whole fleet, so their silicon spreads outward across the system. They build accelerators, yes, but also the memory managers and the networking and the offload chips, because every one of those is a cost they carry at fleet scale.

Vistara is the tell: you only build a chip to rescue old memory if you run millions of servers. The model makers own the model and little else, so their silicon reaches inward, tuning a single accelerator to the shape of their own model, and this is as true in Hangzhou as in San Francisco, DeepSeek and Zhipu shaping parts to their models exactly as OpenAI shapes Jalapeño to its own.

The merchant builders own neither a fleet nor a frontier model, so they make one architectural bet and sell it to whoever will buy, Cerebras and d-Matrix and Tenstorrent and dozens more, alongside larger names like Qualcomm bringing a merchant accelerator to market.

And the fourth group, the one the headlines forget, builds none of its own products at all. It builds the pieces the others assemble, the design partners and the memory-fabric and interconnect specialists and the software floor beneath them all.

Two things separate the first two groups from the rest. They have a moat, because their silicon is wired to plans they control and to demands they already own, and they have visibility, because they can see whether the chip will be used before it exists. The merchant builder has neither. It designs into the dark, betting an outside world will still want its one idea by the time the idea ships.

And here the framework must confess its own limits, which is the point rather than a hedge. It explains only so much. In detail, every one of these efforts is different, many are early and planned inside their own bubble, blind to what rivals are building and why, and some will be obsolete before their first silicon returns from the factory.

That fog, created by the constantly shifting landscape, is the one most underappreciated, even by experts focused on the available details of every plan. If the builders cannot see one another, an outsider certainly cannot rank them from the results of a press release.

The new fablessness

We will need to dial back, as some of the points are already flagged in the primer above. But they need more attention to discern what has changed.

The global business of designing chips without owning a factory is booming, and it has a new class of entrants in the largest modelmakers. They do not aspire to be like classical fabless chip vendors or hyperscalers.

Their labs seem to simply specify the workload, the memory hierarchy, the compiler, and the networking, and rent the rest. They are not becoming chip companies in the old sense. They are becoming companies that shape the chip around the model and outsource everything else.

Their logic, drawing on the points in the primer, is more optimization. For the last two years, the modelmakers squeezed efficiency out of software by splitting model loading using methods like mixtures of experts, fewer active parameters, quantization, and sparser attention.

Each major modelmaker seems to realize that there is more possible if they spread the wings from algorithm to hardware, and the chip stops being something you buy and becomes something you shape.

There is a clear gap in the stage at which different modelmakers are, even if their announcements seem to be coming at the same time in recent days. OpenAI has silicon to show. Anthropic is circling. DeepSeek and Zhipu are early.

One caution against the easy version of this narrative. None of these labs is betting the farm on its own chip. The custom part is a hedge, not the main position. Anthropic runs on rented accelerators today and explores its own for tomorrow, all at once, and the others look similar underneath.

The move is portfolio optimization, not a leap of faith, which is exactly why so many can make it at once without any of them risking much. A side of objective seems to be an eye on the future: any knowledge gained in the chip development could prove valuable as model development evolves.

And it is the sharpest confirmation yet of what Hardware’s Software argued. Chip design has become the part of this industry that behaves like software once did, and it draws a crowd for the same reason software did, because the marginal cost of trying has fallen.

Months versus decades

For Alphabet, the development of Ironwood, released last year and in many ways comparable to NVIDIA’s best, took a decade of building experience. As against this, OpenAI seems to have developed a usable chip for its models in nine months. Even if one is more scrupulous in calculating the latter’s timeline, OpenAI, with its partner Broadcom, has gone from conception to manufacturing tape-out in 18 to 24 months.

Nine months looks like someone collapsed the decade we leaned on in the Real Chip War. It looks like the crutch broke. It did not break. The decade was rented, not skipped.

The timeline gaps reveal the gaps in what is being built. The nine-month chip is a narrow, inference-only part. In addition, it moved fast because the hard, accumulated work was supplied by a partner who had already spent the decade doing it, on top of a collaboration that had itself been running well over a year before the design cycle even began. The lab brought the architecture and used its own models to speed up the work. The partner brought the experience.

For every aspirant, whether from or outside the US, the need to find the right partner is critical. Whether it is DeepSeek or Anthropic, each will need years of accumulated knowledge to field not just a general accelerator but highly specific inference chips of cutting-edge utility. 

As hinted earlier, a custom chip is a frozen bet on a moving target. The field’s dominant architecture can shift under a chip in the two to three years it takes to design and yield one, and a chip optimized for the old shape does not become a weaker rival to the incumbent. It becomes a paperweight.

This is not an argument against custom silicon. It is the argument for where custom silicon will concentrate: on the dullest, most stable, highest-volume inference workloads, the recommendation and ranking and standard serving that do not move, while the frontier, which keeps moving, keeps renting the flexible GPU.

It also draws the boundary of the threat. The narrow chips attack the incumbent’s inference margin. Training is harder to displace because model churn and flexibility still favor the general part.

The constraint Is global, and so is the ingenuity

Denied access to the best parts, the leading Chinese labs co-designed their models around what they had, compressing the memory their models demanded and rewriting the low-level work by hand, then spending more time where they could not spend more compute. The result is frontier-adjacent models at a fraction of the arithmetic.

However, a real efficiency gap persists, and the ingenuity was itself paid for with a great deal of earlier compute. On the serving side, the answer has been to build at the level of the system rather than the chip.

If each accelerator is weaker, wire many more of them together with fast optics and pooled memory, and let the cluster reach in aggregate what a single rack of the best foreign parts would reach. It works, and it spends several times the silicon and the power to get there, which for a country short on both is a permanent tax rather than a free lunch. 

None of this changes the same custom chip ownership logic we described for the US players above: a player that works on the whole system for optimization may have a higher chance of competing at the frontier in the years ahead. The trend being started by DeepSeek and Zhipu is likely to catch on like wildfire, particularly when chip design is no longer seen as an expensive or difficult exercise. 

It will be remiss not to mention the rest in this section on players who are not the largest hyperscalers or modelmakers. A great many private companies are circulating decks full of architectures that will, they promise, undo the incumbent, some by the audacious route of removing high-bandwidth memory from the problem entirely.

A few are serious. Most are a presentation. The distance from a slide to a yielding, deployed part is measured in years and numerous execution risks. For most outside observers, understanding the uniqueness of these plans is nigh impossible, even where substantial design details are available.

For most such companies, the best evaluation will be possible either when they complete their earliest working prototypes or based on the interest they attract from knowledgeable players seeking new IP. Of course, for many investors, such evidence could be too late, but the point remains: it is difficult to assess the value of any custom chips based on investor presentations.

Cleanest beneficiaries in the helpers 

The main point above is that a description of an attempt in chip design, irrespective of where it is coming from, tells you almost nothing about the chip that emerges.

“We are designing a custom inference accelerator” is a shout likely to grow if our arguments on the model optimization in the periods ahead prove true. The announcements will run well ahead of the silicon, and the vocabulary is too blunt to sort them. Anyone trying to estimate the value of a chip design press release faces risks of the unknowable.

Then there will be other words that carry most of the false comfort, like “tape-out.” Tape-out sounds like a finish line, and it is closer to a starting line, but it is perhaps equivalent to phase one in a clinical trial of a new drug.

A tape-out is only the moment a design is declared final and handed to the factory, before the first wafer exists, and it is married to one node at one foundry and usually one packaging flow, not portable to another without months of rework. So the industry announces tape-outs as though the race were won, when all that has happened is that a design has committed itself to a particular queue in the best case, assuming the tests work.

And the queue is the whole problem. Every one of these designs, the hyperscalers’ and the model makers’ and the challengers’ and China’s, still lines up at the same narrow set of fabs and the same gated advanced packaging and the same scarce memory.

A successful prototype is not a product. Many perfectly good chips will never reach volume because the capacity to build them at scale is spoken for, and by the time it frees up, a better-supplied rival has taken the socket. 

For evidence-based investors, the durable value will be with the helpers and not the builders. That more custom design attempts are going to be made is a given. Customization is going to spread with more memory being placed next to logic and more logic being placed next to memory. The pace of growth in interconnect optimization will also remain breathtaking.

The players with the least amount of risks, but substantial volume growth, will be the ecosystem players with moats. These firms carry none of the builder’s specific risks. They do not need any one architecture to win, any one plan to come true, or any one queue to clear in time. They need only for the crowd, in aggregate, to keep trying, and they can diversify across every builder at the table. 

Which returns us to where we began. Saying “we do custom chips now” is becoming as empty as a company announcing “software development” as a new activity around the year 2000. At the rate this is going, it can only be a matter of time before a bank or a consultancy floats its own chip-design aspirations on an earnings call.

In 2000, “we build software” told you someone had a keyboard, not a product. In 2026, “we design silicon” tells you someone has an architecture slide, and perhaps a tape-out, which is to say a place in a queue. The first job is not to be impressed. It is perhaps to identify who they are partnering with for their spend.

Nilesh Jasani is the director and chief executive officer of GenInnov Singapore – the original publisher of this article, which is republished with permission – and a director of the GenInnov Master Fund.